
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   19:21:11 03/16/2012
-- Design Name:   IOclock
-- Module Name:   C:/Prog/CUARTO/AIC/CycloneProject/procesadorcyclone-aic-uspceu-2011-2012/ES/tb_io_clock.vhd
-- Project Name:  entradaSalida
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: IOclock
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.definitions.all;

ENTITY tb_io_clock_vhd IS
END tb_io_clock_vhd;

ARCHITECTURE behavior OF tb_io_clock_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT IOclock
	PORT(
		clk_i : IN std_logic;
		instr_ack_i : IN std_logic;
		instr_word_i : IN std_logic_vector(17 downto 0);
		data_ack_i : IN std_logic;
		data_word_i : IN std_logic_vector(7 downto 0);
		port_ack_i : IN std_logic;
		port_word_i : IN std_logic_vector(7 downto 0);
		cu_status : IN state_type;
		cu_mem_op : IN std_logic;
		ena_mem_port_data : IN std_logic;
		mem_rw : IN std_logic;
		datapath_word_o : IN std_logic_vector(7 downto 0);
		datapath_addr_o : IN std_logic_vector(7 downto 0);
		pc : IN std_logic_vector(9 downto 0);          
		clk_o : OUT std_logic;
		instr_reg : OUT std_logic_vector(17 downto 0);
		data_reg : OUT std_logic_vector(7 downto 0);
		instr_cyc_o : OUT std_logic;
		instr_stb_o : OUT std_logic;
		instr_addr_o : OUT std_logic_vector(9 downto 0);
		data_cyc_o : OUT std_logic;
		data_stb_o : OUT std_logic;
		data_we_o : OUT std_logic;
		data_addr_o : OUT std_logic_vector(7 downto 0);
		data_word_o : OUT std_logic_vector(7 downto 0);
		port_cyc_o : OUT std_logic;
		port_stb_o : OUT std_logic;
		port_we_o : OUT std_logic;
		port_addr_o : OUT std_logic_vector(7 downto 0);
		port_word_o : OUT std_logic_vector(7 downto 0);
		instr_ack_to_cu : OUT std_logic;
		data_ack_to_cu : OUT std_logic;
		port_ack_to_cu : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk_i :  std_logic := '0';
	SIGNAL instr_ack_i :  std_logic := '0';
	SIGNAL data_ack_i :  std_logic := '0';
	SIGNAL port_ack_i :  std_logic := '0';
	SIGNAL cu_status :  state_type:= WRITEBACK;
	SIGNAL cu_mem_op :  std_logic := '0';
	SIGNAL ena_mem_port_data :  std_logic := '0';
	SIGNAL mem_rw :  std_logic := '0';
	SIGNAL instr_word_i :  std_logic_vector(17 downto 0) := (others=>'0');
	SIGNAL data_word_i :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL port_word_i :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL datapath_word_o :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL datapath_addr_o :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL pc :  std_logic_vector(9 downto 0) := (others=>'0');

	--Outputs
	SIGNAL clk_o :  std_logic;
	SIGNAL instr_reg :  std_logic_vector(17 downto 0);
	SIGNAL data_reg :  std_logic_vector(7 downto 0);
	SIGNAL instr_cyc_o :  std_logic;
	SIGNAL instr_stb_o :  std_logic;
	SIGNAL instr_addr_o :  std_logic_vector(9 downto 0);
	SIGNAL data_cyc_o :  std_logic;
	SIGNAL data_stb_o :  std_logic;
	SIGNAL data_we_o :  std_logic;
	SIGNAL data_addr_o :  std_logic_vector(7 downto 0);
	SIGNAL data_word_o :  std_logic_vector(7 downto 0);
	SIGNAL port_cyc_o :  std_logic;
	SIGNAL port_stb_o :  std_logic;
	SIGNAL port_we_o :  std_logic;
	SIGNAL port_addr_o :  std_logic_vector(7 downto 0);
	SIGNAL port_word_o :  std_logic_vector(7 downto 0);
	SIGNAL instr_ack_to_cu :  std_logic;
	SIGNAL data_ack_to_cu :  std_logic;
	SIGNAL port_ack_to_cu :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: IOclock PORT MAP(
		clk_i => clk_i,
		clk_o => clk_o,
		instr_ack_i => instr_ack_i,
		instr_word_i => instr_word_i,
		data_ack_i => data_ack_i,
		data_word_i => data_word_i,
		port_ack_i => port_ack_i,
		port_word_i => port_word_i,
		cu_status => cu_status,
		cu_mem_op => cu_mem_op,
		ena_mem_port_data => ena_mem_port_data,
		mem_rw => mem_rw,
		datapath_word_o => datapath_word_o,
		datapath_addr_o => datapath_addr_o,
		pc => pc,
		instr_reg => instr_reg,
		data_reg => data_reg,
		instr_cyc_o => instr_cyc_o,
		instr_stb_o => instr_stb_o,
		instr_addr_o => instr_addr_o,
		data_cyc_o => data_cyc_o,
		data_stb_o => data_stb_o,
		data_we_o => data_we_o,
		data_addr_o => data_addr_o,
		data_word_o => data_word_o,
		port_cyc_o => port_cyc_o,
		port_stb_o => port_stb_o,
		port_we_o => port_we_o,
		port_addr_o => port_addr_o,
		port_word_o => port_word_o,
		instr_ack_to_cu => instr_ack_to_cu,
		data_ack_to_cu => data_ack_to_cu,
		port_ack_to_cu => port_ack_to_cu
	);

	clk: PROCESS
	begin 
		clk_i <= '1';
		wait for 100 ns;
		clk_i <= '0';
		wait for 100 ns;
	end process;
	

	tb : PROCESS 
	BEGIN
		
		--************ CASO 1 : LECTURA DE MEMORIA DATOS 1 CICLO *************
		-- FETCH
		cu_status <= FETCH;
		pc<="0000000001";
		cu_status<=FETCH; 
		wait for 20 ns; -- respuesta de la memoria
		instr_ack_i <= '1';
		instr_word_i <="000000000000000001";
		wait for 180 ns;
		instr_ack_i <= '0'; --FIN CICLO MEMORIA

		-- DECODE 
		cu_status <= DECODE;
		wait for 200 ns;	

		-- EXECUTE
		cu_mem_op <='1';
		cu_status <= EXECUTE;
		mem_rw <='0';
		ena_mem_port_data <= '0';
		datapath_addr_o <= "11100000";
		wait for 20 ns;  --Comienzo respuesta memoria
		data_word_i<= "11110000";
		data_ack_i<='1';
		wait for 180 ns;
		data_ack_i<='0';  --Fin respuesta memoria

		-- WRITEBACK
		cu_mem_op <='0';
		cu_status <= WRITEBACK;
		wait for 200 ns;
		
	
		--************ CASO 2 : ESCRITURA DE MEMORIA DATOS (PORT) 1 CICLO *************
		-- FETCH
		cu_status <= FETCH;
		pc<="0000000010";
		cu_status<=FETCH; 
		wait for 20 ns; -- respuesta de la memoria
		instr_ack_i <= '1';
		instr_word_i <="000000000011000000";
		wait for 180 ns;
		instr_ack_i <= '0'; --FIN CICLO MEMORIA

		-- DECODE 
		cu_status <= DECODE;
		wait for 200 ns;	

		-- EXECUTE
		cu_mem_op <='1';
		cu_status <= EXECUTE;
		mem_rw <='1';
		ena_mem_port_data <= '1';
		datapath_addr_o <= "11100100";
		datapath_word_o <= "11100110";
		wait for 20 ns;  --Comienzo respuesta memoria
		port_ack_i<='1';
		wait for 180 ns;
		port_ack_i<='0';  --Fin respuesta memoria

		-- WRITEBACK
		cu_mem_op <='0';
		cu_status <= WRITEBACK;
		wait for 200 ns;
		
		
		
		
		--************ CASO 3 : LECTURA DE MEMORIA DATOS (PORT) 2 CICLOs *************
		-- FETCH
		cu_status <= FETCH;
		pc<="0000000011";
		cu_status<=FETCH; 
		wait for 20 ns; -- respuesta de la memoria
		instr_ack_i <= '1';
		instr_word_i <="110000000000000001";
		wait for 180 ns;
		instr_ack_i <= '0'; --FIN CICLO MEMORIA

		-- DECODE 
		cu_status <= DECODE;
		wait for 200 ns;	

		-- EXECUTE
		cu_mem_op <='0';
		cu_status <= EXECUTE;
		wait for 200 ns;
		
		
		-- MEMORIA 
		cu_status <= MEM;
		mem_rw <='0';
		ena_mem_port_data <= '1';
		datapath_addr_o <= "11100111";
		wait for 20 ns;  --Comienzo respuesta memoria
		port_word_i<= "11000000";
		port_ack_i<='1';
		wait for 180 ns;
		port_ack_i<='0';  --Fin respuesta memoria

		-- WRITEBACK
		cu_mem_op <='0';
		cu_status <= WRITEBACK;
		wait for 200 ns;
		
		
		--************ CASO 4 : ESCRITURA DE MEMORIA DATOS  2 CICLOS *************
		-- FETCH
		cu_status <= FETCH;
		pc<="0000000100";
		cu_status<=FETCH; 
		wait for 20 ns; -- respuesta de la memoria
		instr_ack_i <= '1';
		instr_word_i <="000001110011000000";
		wait for 180 ns;
		instr_ack_i <= '0'; --FIN CICLO MEMORIA

		-- DECODE 
		cu_status <= DECODE;
		wait for 200 ns;	

		

		-- EXECUTE
		cu_mem_op <='1';
		cu_status <= EXECUTE;
		wait for 200 ns;	
		
		-- MEMORIA
		cu_status <= MEM;
		mem_rw <='1';
		ena_mem_port_data <= '0';
		datapath_addr_o <= "11111100";
		datapath_word_o <= "11111110";
		wait for 20 ns;  --Comienzo respuesta memoria
		data_ack_i<='1';
		wait for 180 ns;
		data_ack_i<='0';  --Fin respuesta memoria

		-- WRITEBACK
		cu_mem_op <='0';
		cu_status <= WRITEBACK;
		wait for 200 ns;
		
		

		wait; -- will wait forever
	END PROCESS;

END;
